In the first quarter earnings conference call for Synopsys in fiscal year 2025, Trey Campbell, the Senior Vice President of Investor Relations, introduced the session. Present were Sassine Ghazi, President and CEO, and Shelagh Glaser, CFO. Trey emphasized that forward-looking statements made during the call are based on current expectations and subject to uncertainties. He noted that non-GAAP financial measures would be discussed, with supplementary information available on the company's website. Sassine Ghazi reported that the company had a strong start to 2025, surpassing their revenue midpoint guidance and exceeding the non-GAAP EPS guidance range, despite a 4% year-over-year revenue decline and a 10% non-GAAP EPS drop, attributed to having one fewer workweek compared to the previous year.

The paragraph discusses business highlights for Synopsys, noting robust AI and HPC markets in the first quarter, while industrial, automotive, and consumer electronics sectors are facing challenges. Synopsys' opportunities are anchored in R&D and influenced by AI, silicon proliferation, and software-defined systems, which demand new design paradigms due to increasing complexity and costs. The company's strategy includes acquiring ANSYS to enhance AI-powered design solutions, with regulatory approvals progressing. The Design Automation segment saw a 4% year-over-year revenue increase in Q1, despite having one less week of revenue, solidifying Synopsys' leadership in hardware-assisted verification solutions.

This month, Synopsys expanded its industry-leading HAV portfolio with new HAPS 200 prototyping and ZeBu 200 emulation systems, offering up to 2x improved performance over previous models. Major companies like AMD, ARM, NVIDIA, and SI5 are utilizing these new technologies. The company anticipates strong performance this year, following a record year in hardware, due to high demand for its advanced, flexible prototyping and emulation solutions. In EDA software, Synopsys is seeing increased activity at advanced nodes, with notable 2-nanometer projects. The Fusion Compiler platform is prominent in digital design implementation, and was used for a U.S. hyperscaler’s 2-nanometer test chip and other significant tape-outs. Synopsys’ key technologies, including PrimeTime and IC Validator, are highly trusted, providing essential analytical solutions and substantial productivity improvements for customers, with some reporting enhanced turnaround times.

Leading-edge customers are achieving over 2x faster turnaround times for chip physical verification sign-off at 3-nanometer or smaller nodes, allowing design teams to complete more sign-offs within budget. STAR RC, a leading extraction tool for advanced process nodes, is widely used by major CPU and GPU customers for its accuracy and performance. The growing AI infrastructure is transforming industries, including the field of electronic design automation (EDA), where AI-driven capabilities are enhancing productivity and reinforcing Synopsys' leadership. Though initial AI-driven optimizations have not yet significantly changed the chip design flow, a future paradigm shift with agent AI promises major productivity gains. More details will be shared at the Synopsys User Group Conference in March. In Q1, Synopsys continued to promote the adoption of its AI tools in various domains such as design implementation, verification, and analog, noting significant developments in verification with VSO.ai in the U.S.

The paragraph discusses the deployment and impact of VSO.ai and ASO.ai on improving hardware utilization and productivity in tech companies, including a significant performance boost in HPC design and aerospace. Synopsys has expanded its generative AI offerings, adding new script generation capabilities to tools, resulting in productivity improvements for designers. The company's generative formal verification tool has also provided productivity gains. Despite a 17% year-over-year decrease in design IP revenue, the demand for IP continues to grow as AI transitions drive the need for better performance per watt. Synopsys launched new IP solutions like the Ultra Accelerator Link to help scale AI infrastructure and optimized its foundation IP libraries to enhance AI performance. The company's memory and logic libraries have been used for notable breakthroughs in LLM performance at 5-nanometer, as AI accelerates protocol advancements.

In this quarter, the company achieved significant design wins across various sectors, notably in AI infrastructure with a PCIe 7.0 design and securing a 224-gig Ethernet agreement. They also reached deals for 112-gig SerDes and PCIe 6.0 with a European telecom provider and a 2-nanometer interface IP for an automotive OEM. Their IP developments for the foundry ecosystem are essential, and they announced successful silicon results for PCIe 4.05 on Samsung's process, along with a nonvolatile memory IP suitable for secure storage in multiple TSMC processes. Despite challenging demand in the mobile and consumer markets, design activities continue, with a leading Asian automotive supplier and a mobile provider adopting various interface and processor IPs. The company also secured a UFS design linked to AI PCs and sees strong demand for advanced UFS protocols to support AI storage needs. Overall, their business model is robust, with solutions crucial to client innovation and benefiting from AI-driven growth trends.

The paragraph discusses the company's strong start to 2025, highlighting the application of AI in engineering and solid financial performance in the first quarter. Shelagh Glaser reports that the company achieved revenue at the upper end of its guidance, a non-GAAP operating margin of 36.5%, and non-GAAP earnings surpassing expectations. Total revenue reached $1.46 billion, with both GAAP and non-GAAP costs outlined, resulting in non-GAAP earnings of $3.03 per share. The company reaffirms its 2025 targets, aiming for revenue between $6.745 and $6.05 billion and a non-GAAP operating margin of 40% at the midpoint. Additionally, the forecast includes cash flow from operations of around $1.8 billion and free cash flow of $1.6 billion. Further details for the second quarter guidance are to be provided.

The paragraph discusses financial results and projections for a company, highlighting revenue expectations between $1.585 billion and $1.615 billion, with total GAAP costs ranging from $1.19 billion to $1.21 billion, and non-GAAP costs between $985 million and $995 million. The company projects GAAP earnings of $2.21 to $2.33 per share and non-GAAP earnings of $3.37 to $3.42 per share. They aim for a 10.1% to 11.1% revenue growth by 2025, with a non-GAAP operating margin of 3% and approximately 13% non-GAAP EPS growth. The firm expresses confidence due to strong execution and leadership. The discussion then shifts to a Q&A where Sitikantha Panigrahi from Mizuho inquires about growth trends, particularly concerning AI-driven designs, and Sassine Ghazi responds by noting strong demand in semiconductor markets for AI and HPC, indicating a positive outlook for the company amidst the evolving landscape.

The paragraph discusses the shifting opportunities for leveraging AI in different customer sectors, with recent growth in consumer electronics, particularly in PCs and mobile devices, due to AI applications. DeepSeek offers potential for expanding AI adoption on these devices by providing affordable and effective solutions that don't require cloud access. There is an expected increase in semiconductor R&D investment, benefiting Synopsys, which supplies R&D within its customer base. Synopsys also sells to system companies developing chips for internal use, a growing opportunity as they consume IT hardware and software for sophisticated chip design. Sassine Ghazi notes an acceleration in consumer electronics roadmaps for PC and mobile chips, while automotive and industrial sectors remain unchanged. The paragraph concludes with a mention of Chinese market growth flattening, accounting for 12% of sales in the last quarter.

The paragraph discusses Synopsys' business situation in China, highlighting a deceleration in sales due to two main factors: cumulative effects of export restrictions and a slowing local economy affecting start-ups. Despite hardware sales performing well, the company expects China's performance to continue declining below the corporate average into FY '25. The paragraph also touches on Synopsys' interest in Agentic AI, mentioning it as a promising opportunity, though specifics on its impact on operating margins or product development were not detailed.

The paragraph discusses the evolving role of AI in engineering workflows and how Synopsys is partnering with AI providers to integrate these advancements. The company's strategy involves leveraging AI to enhance productivity across various functions beyond just engineering. In a conversation with Joe Quatrochi from Wells Fargo, Sassine Ghazi highlights Synopsys' engagement with semiconductor companies, noting a trend in design activity: AI and high-performance computing projects are accelerating their development timelines, while the consumer electronics and auto-industrial sectors have not experienced the same acceleration. However, there has been observed growth in the mobile and PC markets.

The paragraph discusses the current state and future prospects of the auto and industrial markets, noting a steady pace but ongoing investment in chip development, albeit at a slower rate. Joe Quatrochi asks about the growth trajectory and inventory levels after new hardware solutions are launched. Sassine Ghazi expresses excitement over the launch, emphasizing its focus on hybrid emulation prototyping, where Synopsys has been a leader. Shelagh Glaser reports a 15% quarterly increase in hardware investment and a 9% annual increase, driven by strong demand outpacing supply. The company is working to meet this demand and expects a significant uptick in Q4 hardware availability.

In the paragraph, Charles Shi asks Shelagh Glaser about the backlog for fiscal Q1 '25, which is reported as $7.7 billion. Shi then inquires about Synopsys's EDA revenue growth, noting a slowdown from fiscal '24 and comparing it to peers. He questions whether last year's slowdown represents a cyclical bottom or if further recovery, particularly in non-AI areas, is needed to achieve long-term growth targets. Sassine Ghazi responds, explaining that the EDA market can be volatile quarter-over-quarter but expects a 12% growth over the next five years based on a projected CAGR. He emphasizes that increasing R&D investments by semiconductor companies, a key customer group, are beneficial for Synopsys's growth in hardware, IP, and EDA.

The paragraph discusses the financial outlook and challenges faced by a company, especially regarding its operations in China. The company is experiencing a higher growth rate than anticipated and is comfortable committing to a 12% growth target. However, the revenue in China saw a significant decrease in the first quarter compared to the previous year's average, which raises concerns about reaching projected growth targets in fiscal '25. Sassine Ghazi mentions that due to increasing headwinds and deceleration in China, the company does not expect to meet the corporate average growth there, reflecting this in their guidance. The conversation shifts to backlog positions, indicating a recent trend where more contracts are moving to current balances rather than long-term engagements, which contrasts with historical patterns of strong long-term backlog development.

The paragraph involves a discussion between Sassine Ghazi, Shelagh Glaser, and Joe Vruwink about customer behavior and contract duration in the context of electronic design automation (EDA). Ghazi notes that there has been no significant change in customer behavior or contract durations, even as chip-building timelines may vary. Glaser adds a nuance about backlog reporting, emphasizing that variation is minimal and heavily reliant on customer preference regarding the base contract and future service agreements (FSA), which are non-cancellable and used as needed by customers. Vruwink shifts the discussion to the impact of AI on EDA growth rates, questioning if AI optimizations affect expectations for industry growth rates expressed a year ago.

In the paragraph, Sassine Ghazi discusses the impact of AI technologies on their business. Although the monetization of AI optimization alone may not significantly contribute to the 200 basis points of benefit, combining it with generative and Igentec technologies offers opportunities for enhanced workflow and cost-effective chip design for customers. This makes it possible to monetize the offerings differently. The adoption and customer excitement about these technologies are positive, aligning with their expectations. The conversation then shifts to Jason Celino's question on assumptions about China in the context of guidance given 90 days ago, hinting that below corporate average performance was expected.

In the paragraph, Jason questions whether there's been a positive change in the EDA or IP business since the full-year guidance remains unchanged despite challenges in China. Sassine Ghazi confirms that the company's assumptions and guidance remain the same, noting anticipated challenges in China and clarifying its potential impact on performance. Jason then inquires about the new product announcements, HAPS 200 and ZeBu 200, and concerns about potential gaps in demand as customers await new orders. Aart de Geus explains that their use of FPGA technology allows for quicker product updates, preventing demand gaps, as existing customers are already purchasing both the previous and new generations simultaneously. Shelagh Glaser adds that any concerns were about product availability rather than demand.

The discussion focuses on the concentration of growth among semiconductor companies, with a few experiencing strong growth due to increased investments in R&D, especially in advanced chip development and integration. Sassine Ghazi explains that the company's growth aligns with the industry's investment in R&D, indicating that as semiconductor companies increase their R&D spending from 6% to 9%, the company experiences parallel growth. These investments involve updating IP, using the latest EDA software, and improving hardware, reflecting a broader trend toward more concentrated yet significant growth opportunities within the semiconductor sector.

The paragraph discusses the historical variations in productivity and return on investment among customers using commercial Electronic Design Automation (EDA). Despite significant EDA spending, differences in returns have persisted. With the introduction of AI capabilities into the design process, there's speculation that customer capabilities may become more uniform. Sassine Ghazi notes that AI has not yet altered the design workflow, which has remained consistent despite advancements. He highlights that if AI could change the workflow, there would be potential for new monetization opportunities, akin to trends in other enterprise software sectors. Until now, EDA has delivered technological innovations, but the essential workflow steps have stayed the same.

The paragraph is from a financial earnings call where Nay Soe Naing from Berenberg asks about cost control and guidance for the upcoming quarters, noting a discrepancy between anticipated and actual expense growth. Shelagh Glaser explains that costs in Q1 were lower than expected due to timing of hiring and expenses, but expects no change for the year. Costs will structurally increase in Q2 due to annual merit and performance budgets. Joshua Tilton from Wolfe Research seeks clarification on whether the company's guidance for China has changed, as previously it was expected to grow in line with the corporate average, but now seems to be expected to grow below it.

In the paragraph, Sassine Ghazi addresses concerns about potential growth in China being below the corporate average for FY '25 despite headwinds, such as new customers being added to the entity list, indicating some challenges in that market. However, he emphasizes confidence in the company's overall growth guidance due to strengths in technology and other regions. These strengths include opportunities to monetize intellectual property (IP) and strong demand from system companies, particularly in AI and high-performance computing (HPC), supported by the HAPS 200 and ZeBu 200 product families. Overall, the company views its position and market leadership as advantageous for capitalizing on these opportunities.

The paragraph highlights the importance of advanced EDA (Electronic Design Automation) and AI optimization for chip design, mentioning tools like the Fusion design platform, ICV, and IC Validator. These innovations are boosting confidence in increasing market share and monetization, aligning with the company's guidance. The paragraph concludes with the operator closing the conference call.

This summary was generated with AI and may contain some inaccuracies.